Chip Design and Manufacturing with AI
Thursday, December 05, 2024
AI has been in the center of discussion in many and broad fields of study. Semiconductor chip design and manufacturing are no different.
We will review some of the examples in this domain, and see how AI really can enhance the process.
For chip design, we will cover IR-drop estimation, pre-layout clock tree estimation, placement utilization for low aspect ratio design, PDN impedance analysis of DRAM circuits, etc.
We will focus on lithography process of manufacturing in particular, and address optical proximity correction (OPC), re-fragmentation, lithography modeling, and test pattern synthesis.
Post Talk Link: Click Here
Passcode: P%+C&11i
Speaker/s
Youngsoo Shin is a professor with the School of EE, KAIST, Korea since 2004. He founded a start-up called Baum in 2016; the company has been successful in commercializing EDA SW for chip power analysis and optimization. He is an IEEE Fellow.
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